1. Field of the Invention
The present invention relates to a Delay Locked Loop (DLL), and more particularly, to a DLL with multi-phases.
2. Description of the Related Art
A semiconductor device, which processes signals at high speed with a built-in memory, uses a Phase Locked Loop (PLL) or a Delay Locked Loop (DLL) in order to synchronize input/output data with a system clock. The DLL features less jitter and is simpler and more reliable than the PLL. However, the DLL is disadvantageous in that it has limited phases when compared to the PLL. Recently, various methods to overcome the disadvantage of the DLL have been studied. Since the DLL operates reliably even in the digital block where power noise is serious, it has had a wide range of applications.
FIG. 1 is a block diagram of an existing DLL. Referring to FIG. 1, the existing DLL 101 includes a phase comparator 111, an electric charge pump 121, a filter 131 and a delay element 141. The phase comparator 111 compares the phases of an input clock signal (CLKIN) and an output clock signal (CLKOUT). Then, the phase comparator outputs the phase difference as the 1st signal (UP) or the 2nd signal (DN). The electric charge pump 121 increases or decreases the output voltage (V1) depending on the 1st signal (UP) or the 2nd signal (DN). The filter 131 eliminates AC included in the output voltage (V1). The delay element 141 reduces or extends the delay time of the output clock signal (CLKOUT) depending on the output voltage of the filter 131 to be synchronized with or frequency-adjusted with the input clock signal (CLKIN).
In the existing DLL 101, the limited phase capture range may cause harmonic lock.
FIG. 2A shows the output clock signal of the DLL 101 shown in FIG. 1 synchronized with the input clock signal (CLKIN). The rising edge (r1) of the output clock signal (CLKOUT) is synchronized with the rising edge (r2) of the input clock signal (CLKIN) after N clock periods (TN).
FIG. 2B shows the output clock signal (CLKOUT) shown in FIG. 1 in a harmonic lock state. The rising edge (r3) of the output clock signal (CLKOUT) is synchronized with the rising edge (r4) of the input clock signal (CLKIN) after N clock periods (TN). Even though the rising edge (r3) of the output clock signal (CLKOUT) is synchronized with the rising edge of the input clock signal (CLKIN) after N clock periods, the output clock signal is in a frequency-varied harmonic lock state which is an abnormal state. However, the phase comparator 111 judges the state as normal. This is a problem of the existing DLL 101.
IEEE J. Solid-state Circuits, vol 32, pp.1683-1692, Nov 1997 specifies a method of starting the delay line with the minimum delay in the initial operation of the DLL, as a solution to harmonic lock. However, the method specified in the publication can only address harmonic lock in part, and is not a fundamental solution to harmonic lock.
U.S. Pat. No. 5,663,665 discloses another method to resolve harmonic lock. The phase discriminator of the ""665pPatent detects whether the rising edge of the signal of the last tab of the delay element is the same as that of one signal of the middle tabs. If the phase discriminator detects that case, it judges that harmonic lock is present, and prevents harmonic lock by adjusting the delay speed. However, if none of the rising edges of the signals of the middle tabs is the same as the rising edge of the signal of the last tab, the phase discriminator defined in the ""665 patent cannot detect the phase difference and harmonic lock cannot be prevented.
In addition, in some cases, the DLL user requires a randomly delayed clock signal. However, the existing DLL delays the output clock signal only for a pre-defined time.
To solve the above-described problems, it is a first object of the present invention to provide a Delay Locked Loop (DLL) that completely prevents harmonic lock.
It is a second object of the present invention to provide a DLL that can selectively output randomly delayed clock signals.
In accordance with the present invention, there is provided a delay locked loop comprising: a delay unit for receiving an input clock signal, generating an output clock signal whose phase lags that of the input clock signal, and generating multiple delay signals having different phase delays in response to the input clock signal; a harmonic lock preventing unit for receiving the input clock signal and the multiple delay signals, comparing the phases of the input clock signal and the delay signals, generating a 1st signal or a 2nd signal depending on the comparison result, and outputting the 1st signal or the 2nd signal; an electric charge pump for receiving the 1st signal and the 2nd signal, generating a phase control signal, and making the voltage of the phase control signal higher or lower than a pre-defined voltage in response to the 1st signal and the 2nd signal; a filter for eliminating AC included in the phase control signal and transmitting the filtered signal to the delay unit; and start-up circuits for feeding a 1st voltage to the electric charge pump in the initial state before the output clock signal is generated and making the electric charge pump provide a 2nd voltage to the delay unit, wherein the delay unit provides a delay locked circuit that adjusts the phases of the output clock signal and the multiple delay signals in response to the phase control voltage.
Preferably, the delay unit includes: multiple delay elements connected in series for delaying the input clock signal, and outputting the output clock signal and the multiple delay signals; and a bias unit for controlling the delay amount of the multiple delay elements depending on the voltage of the output signal of the filter. Preferably, the multiple delay signals are output from specific elements of the multiple delay elements.
Preferably, the harmonic lock preventing unit includes: multiple phase detectors for comparing two adjacent signals out of the input clock signal and multiple delay signals, activating the 1st signal if the phase is found to lag and activating the 2nd signal if the phase is found to lead, and receiving two adjacent signals out of the input clock signal and the multiple delay signals; a 1st NOR gate and a 2nd NOR gate for each receiving the outputs of half of the multiple phase detectors; an OR gate for receiving the outputs of the 1st NOR gate and the 2nd NOR gate and outputting the 1st signal; and an AND gate for receiving the outputs of the 1st NOR gate and the 2nd NOR gate and outputting the 2nd signal. Preferably, the phase detectors include: a 1st delay flip-flop for receiving the power voltage and the input clock signal or the 1st delay signal and generating the output of the phase detector; a 2nd delay flip-flop for receiving the power voltage and the 2nd delay signal which has a phase closest to that of the 1st delay signal; and a 2nd NAND gate for receiving the outputs of the 1st delay flip-flop and the 2nd delay flip-flop, and providing the outputs to the 1st delay flip-flop and the 2nd delay flip-flop. In addition, preferably, the electric charge pump makes the voltage of the phase control signal higher than the pre-defined voltage if the 1st signal is activated, and makes the voltage of the phase control signal lower than the pre-defined voltage if the 2nd signal is activated. The electric charge pump includes a 1st transistor which outputs a power voltage and is gated by the output of the start-up circuit.
Preferably, if the phase control voltage becomes higher than the pre-defined voltage, the phases of the output clock signal and multiple delay signals are advanced. If the phase control voltage becomes lower than the pre-defined voltage, the phases of the output clock signal and multiple delay signals are delayed. Preferably, the start-up circuit includes: a 1st delay flip-flop for receiving the input clock signal and the output clock signal; and a 2nd delay flip-flop for receiving the outputs of the 1st delay flip-flop and the output clock signal and generating the output of the start-up circuit. Preferably, if the output clock signal is logic low in the initial state before the output clock signal is generated, the start-up circuit outputs the logic low, the 1st transistor is turned on and the power voltage is provided to the filter so that the output clock signal can be quickly synchronized with the input clock signal.
In accordance with a second aspect of the present invention, there is provided a delay locked loop comprising: a delay unit for receiving an input clock signal, generating an output clock signal whose phase lags the input clock signal, and generating 1st multiple delay signals and 2nd multiple delay signals having different phase delays in response to the input clock signal; a harmonic lock preventing unit for receiving the input clock signal and the 1st multiple delay signals, outputting a 1st signal and a 2nd signal, comparing the phases of the input clock signal and the 1st multiple delay signals, and generating the 1st signal or the 2nd signal depending on the comparison result; an electric charge pump for receiving the 1st signal and the 2nd signal, generating a phase control signal, and making the voltage of the phase control signal higher or lower than a pre-defined voltage in response to the 1st signal and the 2nd signal; a filter for eliminating AC included in the phase control signal and transmitting the filtered signal to the delay unit; and a decoder for decoding a received address signal and providing the decoded signal to the delay unit, wherein the delay unit selectively outputs some of the 2nd multiple delay signals in response to the decoded signal and provides a delay locked circuit that adjusts the phases of the output clock signal and the 1st multiple delay signals in response to the output signal of the filter.
Preferably, the delay unit includes: multiple delay elements connected to the input clock signal in series; a bias unit for controlling the delay amount of the multiple delay elements depending on the voltage of the output signal of the filter; and multiple switching elements, connected respectively to the outputs of the delay elements and switched by the decoded signal, for outputting the 2nd multiple delay signals, wherein the 1st multiple delay signals are output by specific elements of the delay elements. It is preferable that the switching elements are transmission gates.
Preferably, the number of 2nd multiple delay signals is larger than the number of 1st multiple delay signals.
In accordance with another aspect of the present invention, there is provided a delay locked loop comprising: a delay unit for receiving an input clock signal, generating an output clock signal whose phase lags the input clock signal, and generating 1st and 2nd multiple delay signals having different phase delays in response to the input clock signal; a harmonic lock preventing unit for receiving the input clock signal and the 1st multiple delay signals, outputting a 1st signal and a 2nd signal, comparing the phases of the input clock signal and the 1st multiple delay signals and generating the 1st signal or the 2nd signal depending on the comparison result; an electric charge pump for receiving the 1st signal and the 2nd signal, generating a phase control signal, and making the voltage of the phase control signal higher or lower than a pre-defined voltage in response to the 1st signal and the 2nd signal; a filter for eliminating AC included in the phase control signal and transmitting the filtered signal to the delay unit; start-up circuits for feeding a 1st voltage to the electric charge pump in the initial state before the output clock signal is generated and making the electric charge pump provide a 2nd voltage to the delay unit; and a decoder for decoding a received address signal and providing the decoded signal to the delay unit, wherein the delay unit selectively outputs 2nd multiple delay signals in response to the decoded signal and adjusts the phases of the output clock signal and 1st multiple delay signals in response to the output signal of the filter. The present invention can prevent harmonic lock.